The present invention relates to interposers that are used to electrically connect various types of substrates to one another, such as to connect integrated-circuit chips to multichip substrates (e.g., multichip modules or printed-circuit boards), or to connect multichip substrates to various types of substrates, such as printed-circuit boards and other multichip substrates.
The present invention is applicable to the electronics packaging arts where several integrated-circuit (I.C.) chips are mounted to one or more substrates, and are interconnected to one another and other components through electrical traces carried by the substrates. The substrates may range from multichip modules, which may hold a few chips to tens of chips, to printed-circuit boards, which may hold tens of chips to hundreds of chips. The chips may be mounted to either multichip modules or printed-circuit boards, and multichip modules are sometimes mounted to printed-circuit boards (at the opposite surface from where the chips are mounted). The chips may be interconnected to one another to form any type of electronic digital system, analog system, or combined analog-digital system, as the application may require. The present invention is not limited to any type of application, or any types of substrates. (As used herein, the term xe2x80x9celectrical componentxe2x80x9d encompasses integrated circuits, multichip modules, printed-circuit boards, and the like.)
Usually, an interposer is needed between an integrated-circuit chip and a main interconnect substrate. A typical prior art interposer comprises a single substrate that is positioned between the chip and the main interconnect substrate, and a plurality of electrical connectors which convey electrical signals between the chip and the main interconnect substrate. Typically, the connector comprises a set of solder bumps that are disposed on corresponding pads on each surface of the interposer, with these solder bumps being reflowed so as to connect to corresponding pads on the I.C. chip and main interconnect substrate. There are a plurality of vias formed through the interposer""s substrate, each via providing an electrical path between two pads on respective surfaces of the interposer""s substrate.
The purpose of the interposer is to provide a tested and reliable package of one or more integrated circuits which can be mounted on the main interconnect substrate in known working condition. The pretesting of the chip reduces the need for reworking of the main interconnect substrate that would normally occur if the chips were directly mounted to the main interconnect substrate. Also, the interposer can accommodate the phenomenon of xe2x80x9cI.C. shrinkxe2x80x9d so there is no need to redesign the layout of the main interconnect substrate when the dimensions of the I.C. chips shrink or change. The xe2x80x9cI.C. shrinkxe2x80x9d phenomenon is the replacement of an existing chip with a smaller chip at a later time by the manufacturer, usually in one to two years. Due to advances in semiconductor processing techniques, the dimensions of transistor devices have progressively decreased over the last three decades. By all indications, these dimensions will continue to decrease in the coming years. Decreasing the size of the transistors enables the chip manufacturer to provide the same circuit functionality on a smaller chip.
When the I.C. chip is powered on and off, prior art interposers often have the problem that their dimensions expand and contract at a different rate than the dimensions of either the I.C. chip or the main interconnect substrate. This difference causes mechanical stresses to be applied to the sets of solder bumps (or other connectors) that are disposed on the two surfaces of the interposer, particularly those bumps that are disposed near the edges of the interposer. This same problem occurs when the I.C. chip is directly mounted to a main interconnect substrate, and is due to the fact that the I.C. chip and the main interconnect substrate are made from different materials which usually have different coefficients of thermal expansion (abbreviated in the art as xe2x80x9cCTExe2x80x9d). For example, silicon chips have a CTE of 2.5 ppm/xc2x0 C., whereas conventional printed-circuit boards have CTEs of between 16 ppm/xc2x0 C. and 18 ppm/xc2x0 C. (ppm represents xe2x80x9cparts-per-millionxe2x80x9d, 1xc3x9710xe2x88x926). If the chip and the main interconnect substrate do not have the same CTE, then the interposer cannot have a CTE which is the same for both the chip and the main interconnect substrate. In the typical case where the I.C. chip and the main interconnect substrate have different CTEs, the interposer will usually have a CTE which is somewhere in the range between the CTEs of the chip and main board, and may even have the same CTE as either the chip or the main board.
By thermal simulation or experimental measurement, one can determine the steady-state temperatures of the I.C. chip, interposer, and the main interconnect substrate for typical operating conditions. With this information and the CTE values of the chip and the main interconnect substrate, one can select a CTE value (and corresponding material composition) for the interposer which causes the thermally-induced stress to be equally distributed among the two sets of solder bumps on either surface of the interposer. While this approach balances the stresses that occur during steady-state conditions, it does not fully minimize the stresses that occur during power-on and power-off conditions, where the temperatures of the components are undergoing transient changes before reaching their steady-state values. Considerable stress can occur during these times, which can cause the solder bumps to fail (due to metal fatigue) after a number of power-on/off cycles, regardless of the stresses that are present during steady-state operations.
Accordingly, there is a need for further improving the thermally-induced stress characteristics of interposers.
The present invention encompasses interposers capable of electrically coupling a first electrical component to a second electrical component and methods for making such interposers. An exemplary interposer according to the present invention comprises a first substrate and a second substrate, each substrate having a first surface, a second surface, and a respective coefficient of thermal expansion (CTE), as measured at the substrate""s respective first surfaces. The exemplary interposer further comprises a plurality of electrical connection areas located over the first surface of the first substrate, another plurality of electrical connection areas located over the first surface of the second substrate. The exemplary interposer further comprises a flexible-circuit layer disposed between each of the first and second substrates, and having a first portion attached to the first surface of the first substrate and a second portion attached to the first surface of the second substrate. The exemplary interposer further comprises a plurality of electrical traces, each trace having a first end located at a connection area over the first substrate, and a second end located at a connection area over the second substrate, with each trace passing through the flexible-circuit layer. The trace ends, which are located at the connection areas, are capable of receiving connectors that will convey electrical signals to the electrical components that are disposed on either side of the interposer.
The coefficients of thermal expansion of the first and second substrates are different from one another (as measured at the first surfaces of the substrates), and are selected to reduce the mechanical stresses of the connectors that are to be mechanically coupled to the trace ends of the interposer.
General methods of making the interposers comprise the step of encapsulating a first substrate and a sacrificial substrate in an encapsulant material to form a composite substrate. The second substrate may be formed from a portion of the encapsulate material, or may be provided by a separate substrate that is encapsulated along with the first substrate and the sacrificial substrate. A first surface of the composite substrate may be polished, and a dielectric layer is formed over the first surface of the composite substrate. A plurality of electrical traces are formed over the dielectric layer. Additional alternating layers of dielectric and metal may be formed over the electrical traces. A portion of the composite substrate at its back surface is removed to expose a surface of the sacrificial substrate, and the sacrificial substrate is removed.
Accordingly, it is an object of the present invention to reduce thermally-induced stress on the connectors that are coupled to interposers.
It is another object of the present invention to enable the increase in the area of a chip that can be electrically connected to a printed-circuit board, multichip module substrates, or the like having a different coefficient of thermal expansion.
It is a further object of the present invention to enlarge the selection of solders and other connection materials which may be used to electrically couple chips, printed-circuit boards, multichip modules substrates, and the like to one another.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, the accompanying drawings, and the appended claims.